TFORIEN=DISABLED, RFORIEN=DISABLED, SPIEN=DISABLED, RESET=INACTIVE, RFRQIEN=DISABLED, MSTEN=DISABLED, TFTH=ONE, RFTH=ONE, DMAEN=DISABLED, TFRQIEN=DISABLED, DDIRSEL=MSB_FIRST, MDFIEN=DISABLED, NSSMD=3_WIRE_MASTER_SLAVE, NSSPOL=LOW, SREIEN=DISABLED, CLKPOL=LOW, URIEN=DISABLED, SLVSELIEN=DISABLED, CLKPHA=CENTER
Module Configuration
| RFRQIEN | Receive FIFO Read Request Interrupt Enable. 0 (DISABLED): Disable the receive FIFO request interrupt. 1 (ENABLED): Enable the receive FIFO request interrupt. |
| RFORIEN | Receive FIFO Overrun Interrupt Enable. 0 (DISABLED): Disable the receive FIFO overrun interrupt. 1 (ENABLED): Enable the receive FIFO overrun interrupt. |
| TFRQIEN | Transmit FIFO Write Request Interrupt Enable. 0 (DISABLED): Disable the transmit FIFO data request interrupt. 1 (ENABLED): Enable the transmit FIFO data request interrupt. |
| TFORIEN | Transmit FIFO Overrun Interrupt Enable. 0 (DISABLED): Disable the transmit FIFO overrun interrupt. 1 (ENABLED): Enable the transmit FIFO overrun interrupt. |
| SLVSELIEN | Slave Selected Interrupt Enable. 0 (DISABLED): Disable the slave select interrupt. 1 (ENABLED): Enable the slave select interrupt. |
| MDFIEN | Mode Fault Interrupt Enable. 0 (DISABLED): Disable the mode fault interrupt. 1 (ENABLED): Enable the mode fault interrupt. |
| URIEN | Underrun Interrupt Enable. 0 (DISABLED): Disable the underrun interrupt. 1 (ENABLED): Enable the underrun interrupt. |
| SREIEN | Shift Register Empty Interrupt Enable. 0 (DISABLED): Disable the shift register empty interrupt. 1 (ENABLED): Enable the shift register empty interrupt. |
| SPIEN | SPI Enable. 0 (DISABLED): Disable the SPI. 1 (ENABLED): Enable the SPI. |
| MSTEN | Master Mode Enable. 0 (DISABLED): Operate in slave mode. 1 (ENABLED): Operate in master mode. |
| CLKPOL | SPI Clock Polarity. 0 (LOW): The SCK line is low in the idle state. 1 (HIGH): The SCK line is high in the idle state. |
| CLKPHA | SPI Clock Phase. 0 (CENTER): The first edge of SCK is the sample edge (center of data bit). 1 (EDGE): The first edge of SCK is the shift edge (edge of data bit). |
| NSSPOL | Slave Select Polarity Select. 0 (LOW): NSS is active low. 1 (HIGH): NSS is active high. |
| DDIRSEL | Data Direction Select. 0 (MSB_FIRST): Data will be shifted MSB first. 1 (LSB_FIRST): Data will be shifted LSB first. |
| NSSMD | Slave Select Mode. 0 (3_WIRE_MASTER_SLAVE): 3-wire Slave or 3-wire Master. 1 (4_WIRE_SLAVE): 4-wire slave (NSS input). This setting can also be used for multi-master configurations. 2 (4_WIRE_MASTER_NSS_LOW): 4-wire master with NSS low (NSS output). 3 (4_WIRE_MASTER_NSS_HIGH): 4-wire master with NSS high (NSS output). |
| RFTH | Receive FIFO Threshold. 0 (ONE): A DMA / RFRQ request asserts when >= 1 FIFO slot is filled. 1 (TWO): A DMA / RFRQ request asserts when >= 2 FIFO slots are filled. 2 (FOUR): A DMA / RFRQ request asserts when >= 4 FIFO slots are filled. 3 (FULL): A DMA / RFRQ request asserts when all FIFO slots are filled. |
| TFTH | Transmit FIFO Threshold. 0 (ONE): A DMA / TFRQ request asserts when >= 1 FIFO slot is empty. 1 (TWO): A DMA / TFRQ request asserts when >= 2 FIFO slots are empty. 2 (FOUR): A DMA / TFRQ request asserts when >= 4 FIFO slots are empty. 3 (EMPTY): A DMA / TFRQ request asserts when all FIFO slots are empty. |
| DSIZE | Data Size. |
| DMAEN | DMA Enable. 0 (DISABLED): Disable DMA requests. 1 (ENABLED): Enable DMA requests according to the TFRQI and RFRQI flags. |
| RFIFOFL | Receive FIFO Flush. 1 (SET): Flush the receive FIFO. |
| TFIFOFL | Transmit FIFO Flush. 1 (SET): Flush the transmit FIFO. |
| RESET | Module Soft Reset. 0 (INACTIVE): SPI module is not in soft reset. 1 (ACTIVE): SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware. |